1. Field of the Invention
This invention relates to MOS device having LDD structure and manufacturing method therefor, in particular to a semiconductor memory device having a dual gate structure such as an EEPROM structure.
2. Description of the Background Art
Conventionally, integration density of semiconductor devices has been increased by miniaturizing the structure of the devices by virtue of the development of the fine processing technique. In a MOS type field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor; hereinafter referred to as a MOSFET), a gate length is shortened from the order of microns to the order of submicrons as the device structure has been miniaturized. As the gate length become shorter, the channel length also becomes shorter, causing a commonly called short channel effect. More specifically, as the channel length becomes shorter, the electric field concentrates near the drain, and therefore the generation of hot carriers has become a serious problem. The hot carriers enter the gate oxide film, causing changes of the threshold voltage on time basis degrading mutual conductance, thereby damaging the reliability of the MOSFET.
EEPROM (Electrically Erasable and Programmable Read Only Memory) is one of memory devices using MOSFETs, which is used in a microcomputer or the like.
FIG. 9 is a block diagram showing a widely known conventional EEPROM which provides for writing and erasure of electrical information or data.
Referring to FIG. 9, the EEPROM includes a memory array 50, comprised of EEPROM cells, a row address buffer 51 receiving a row address signal from outside, a column address buffer 52 receiving a column address signal, a row decoder 53 and a column decoder 54 decoding these address signals and applying an electrical voltage to word and bit lines connected to specified memory cells, a sense amplifier 56 reading a signal stored in the memory cell designated by the two decoders via a Y gate 55, an output buffer 57 for outputting read out data and a control signal input buffer 58 receiving control signals from outside and supplying the control signal to other components.
In operation, the sense amplifier 56 operates to amplify a signal stored in a memory cell to supply the amplified signal to the output buffer 57. FIG. 10 is a circuit diagram showing an example of the memory array 50 and the Y gate 55 shown in FIG. 9.
Referring to FIG. 10, the Y gate 55 includes a transistor 60 connected between an I/O line 59 and a bit line 31 and a transistor 63 connected between a CG line 61 and a control gate line 62. A Y gate signal Y2 is supplied to the gate of transistors 60 and 63. Two unnumbered transistors supplied with a Y gate signal Y1 are connected in a similar manner.
In the memory cell 50, 4 bit memory cells are shown. Each memory cell includes memory transistor 6 having a floating gate and a selection transistor 3 having its gate connected to a word line 32 and supplying a signal stored in the memory transistor 6 to bit line 31. Another selection transistor 3a has its gate connected to a word line 32, and is connected to transmit a signal on control gate line 62 to the gate of memory transistor 6.
In operation, memory transistor 6 stores binary signals depending on whether or not electrons are stored in its floating gate. When electrons are stored therein, the threshold voltage of memory transistor is raised. This turns off memory transistor 6 for the reading operation. When electrons are not stored, the threshold voltage of memory transistor 6 is negative to turn on memory transistor 6 for the reading operation.
The readout voltage from a junction is applied via transistor 6 to bit line 31 and hence to memory transistor 6 via selection transistor 3. Thus it becomes possible to detect at a sense amplifier whether or not the current flows in memory transistor and in this manner to read out the signal stored in memory transistor 6.
FIG. 11 is a plan view of a conventional EEPROM having a floating gate, and FIG. 12 is a cross-sectional view taken along section line XII--XII in FIG. 11. The arrangement of the EEPROM is herein after explained by referring to FIGS. 11 and 12.
The EEPROM includes the memory transistor 6 and the selection transistor 3 both formed on the planar surface of a P type silicon semiconductor substrate. The memory transistor 6 includes a tunnel impurity diffusion layer 9, proving to be a drain region on the planar surface of the semiconductor substrate 20, a tunnel insulating film 16 of a reduced film thickness formed in a predetermined region on a floating gate 14 formed at least in a region inclusive of the tunnel insulating film 16 by the interposition of an insulating film 17, and a control gate 7 formed on the floating gate 14 with the interposition of an interlayer silicon oxide film 15. The overlapping region of control gate 7, floating gate 14 and the interlayer silicon oxide film 15 therebetween constitutes a capacitance C1. The floating gate 14, the tunnel impurity diffusion layer 9 connected to a connecting impurity diffusion layer 5 and the tunnel insulating film 16 constitute a capacitance C2. In a region excluding tunnel insulating film 16, the floating gate 14, the semiconductor substrate 20 and the insulating film in the vicinity of the tunnel insulating film 16 also constitute a capacitance C3. The floating gate 14 accumulates electrical charges. Depending on the voltage applied across the control gate 7 and the connecting impurity diffusion layer 5, the electrical charges are ejected and/or injected between the floating gate 14 and the tunnel impurity diffusion layer 9 by way of tunnel insulating film 16. The selection transistor 3 includes the connecting impurity diffusion layer 5 and a drain region 1 formed on the surface of the semiconductor substrate at some distance from each other, with a selection gate electrode 4 being formed therebetween so as to function as a word line. A selection gate silicon oxide film 13 is formed between the selection gate electrode 4 and the planar surface of the semiconductor substrate 20. The drain region 1 is connected to bit line 31 via a contact hole 11.
The operation of the EEPROM is hereinafter explained. The EEPROM has three basic operating modes of readout, erasure and writing.
The following table tabulates the voltages applied to respective circuit portions or components during writing, erasure or readout of information charges into or from floating gate 14,
TABLE ______________________________________ Circuit Portions or Components readout erase writing ______________________________________ selection gate 5 V V.sub.pp V.sub.pp electrode 4 control gate 7 0 V V.sub.pp OV bit line 31 2 V 0 V V.sub.pp source line 12 0 V floating floating gate 14 V.sub.F V.sub.E V.sub.W ______________________________________
In the above Table V.sub.PP stand for a program voltage, V.sub.F stand for a potential during floating and V.sub.W, V.sub.E stand for the potentials at the floating gate 14 during the operations.
As shown in the above Table, during readout, a voltage of 5V is applied to selection gate electrode 4 and a voltage of 2V is applied to bit line 31, whereas the control gate 7 and the source line 12 are grounded.
During erasure of the memory cell, V.sub.PP, is applied to selection gate electrode 4, whereas bit line 31 and source line 12 are grounded. During this erasure cycle, positive electrical charges are applied to floating gate 14.
During writing, V.sub.PP is applied to selection gate electrode 4 and bit line 31 and the control gate 7 is grounded, whereas the source line 12 is in the floating state. This causes negative electrical charges to be extracted from floating gate 14.
With such EEPROM, technical evolution is now under way with an aim towards enhancing the storage capacity. That is, high integration of the EEPROM are now being promoted with miniaturization of the element structure. One of the impediments in the way of miniaturization of the element structure is the phenomenon know as the hot electron effect, in which electrons called hot electrons are injected into the gate oxide film. In miniaturizing the EEPROM, hot electron effect is supposed to be produced in, for example, the reading transistor 10 shown in FIG. 12. That is, as the reading transistor structure becomes smaller in size, a high electrical field is generated in the vicinity of the tunnel impurity diffusion layer 9 and the electrons generated by ionization caused by collision are partially captured by a trap in the gate oxide film 17 so as to act as negative charges. These negative charges give rise to lowered operational reliability, such as fluctuations in the transistor threshold voltage or lowering in the channel conductance. Should the threshold voltage of the reading transistor 10 be fluctuated under such hot electron effect, there is a risk that the malfunction of the reading transistor be caused during reading of the stored data. Such malfunction of the reading transistor 10 detracts from the reliability as the memory and presents a serious problem to the EEPROM.
Meanwhile, in the field of the MOSFET, a so-called lightly doped drain structure (LDD structure) is generally known as the structure preventing such hot electron effect. The LDD structure is generally formed by a side wall spacer formed on a side wall of a gate electrode. At present, since the problem caused by the hot electron effect produced in the reading transistor 10 in the EEPROM is not so serious, no example can be found which applies the LDD structure to a read transistor of an EEPROM. The interlayer silicon oxide film 15 of the read transistor having a dual gate structure shown in FIG. 12 is formed by a thermal oxidation method. Such a high temperature process as a thermal oxidation method destroys the thin tunnel oxide film 16.
In the EPROM, a structure similar to the LDD structure is applied for a certain other object, as disclosed in the JP Patent Laying-Open No. 62-140472 (1987).